Financial Daily from THE HINDU group of publications
Thursday, May 13, 2004
Financial Daily from THE HINDU group of publications Thursday, May 13, 2004 |
||
|
|
||
|
Industry & Economy
-
Science & Technology IIT develops chipsets on Cadence platform Our Bureau
Kolkata , May 12 STUDENTS of Indian Institute of Technology, Kharagpur's VLSI Design Lab have successfully taped out complete analogue, RF and mixed signal chipsets using the Cadence Virtuoso custom design platform. These chipsets are targeted primarily at the communications and power supply markets. This was announced here today at a press conference that was jointly addressed by representatives of Indian Institute of Technology, Kharagpur (IIT-KGP) and Cadence Design Systems (I) Pvt Ltd. According to Prof P.P. Chakrabarti, Dean of the Sponsored Research & Industrial Consultancy unit of IIT-KGP, the tapeouts have provided students of IIT-KGP's electronics, electrical and computer science departments experience in end-to-end design, allowing them to translate theoretical knowledge into practical chip design. Prof Chakrabarti described the development as a "significant milestone" and said industry and academia would work more closely in the future with a view to ensuring that the fruits of research find commercial application in industry. To facilitate the process, IIT-KGP and Cadence have decided to jointly run undergraduate and post-graduate courses in chip design.
More Stories on : Science & Technology | Hardware
Article E-Mail :: Comment :: Syndication :: Printer Friendly Page
|
Stories in this Section |
|
The Hindu Group: Home | About Us | Copyright | Archives | Contacts | Subscription Group Sites: The Hindu | Business Line | Sportstar | Frontline | The Hindu eBooks | The Hindu Images | Home |
Copyright © 2004, The
Hindu Business Line. Republication or redissemination of the contents of
this screen are expressly prohibited without the written consent of
The Hindu Business Line
|