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Bangalore , Sept. 26

CALIFORNIA-based Synopsys Inc, provider of electronic design automation (EDA) software, has announced that it has partnered with ARM for a book - the Verification Methodology Manual (VMM) for SystemVerilog.

The book details with functional verification techniques that are used by industry experts for complex chip designs. It will be available through publishers Springer Science + Business Media for $129.

The manual also includes the specification for a standard set of libraries for assertions and commonly used verification functions.

The source code for this VMM Standard Library has now been made `open' by Synopsys. SystemVerilog is a fairly new hardware language for design and verification of chip designs. It helps engineers perform advanced verification of chip designs and also reduces the number of lines of code.

The company also announced a new verification tool - Discovery Pioneer-NTB. This is an automation tool built on SystemVerilog will be offered to current users as a free upgrade.

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