The Hindu Business Line : Cadence upgrades EDA platform

Cadence has unveiled Virtuoso, an update on its electronic design & automation (EDA) software platform for chip design. The new platform can save up to 2-4 weeks of design time, considering time taken for individual tasks.

Design methodology has changed over the years, bringing a host of challenges for designers, such as how to maintain original design intent throughout the complete production cycle while managing a global design chain; the unification of different data types, tools and methodologies in a project and the current shortage of experienced analog engineers, which can cause serious project delays, said Mr Steven Lewis - Product Marketing Director, Cadence Design Systems, speaking to told Business Line recently.

Virtuoso solves the design intent problem by adding more constraints (specifications) in the software. Many times, big chip multinationals have cancelled their plans due to missteps in the chip design process. Software can help reduce risk for these companies. It can also help trainees avoid mistakes by capturing the original idea in the form of design constraints. This will work better than explaining the design to the junior either in a schematic or on a phone call, said Mr Lewis. Virtuoso also allows real-time tracking of changes, which is relevant for managing a global design chain. The user interface (UI) of Virtuoso has also been modified to offer a single window for all inter-dependant software.

"There's no looking back, we have modernised the UI to make a new cockpit. There has been no change in the UI for 10-12 years, and this will definitely help the designer," said Mr Lewis.

The update took two 2 years to develop, Mr Lewis he added. Changing the database to open standards - OpenAccess - is another major change in the platform. Now, the platform allows for IP re-use, making it more compatible and developer-friendly.

Smaller Chips

"As chips get smaller, verification tools have to also be able to gulp down the design geometries. Simulation models better represent 65 nm designs," said Mr Lewis. With Virtuoso's resolution enhancement technology suite, bolder designs will ensure that the design comes through exactly as envisioned.

Future plans for Cadence include adding electrical characteristics to the constraints to make designing more exact. The Virtuoso division also plans to conduct research in wireless space and the cross-discipline needs of RF and analogue domains.

The company is offering the software in flexible licensing options. In the tier model, the L package offers basic C programming while XL offers assistance for mundane tasks as well as design constraints. The most advanced version, GXL, will offer extra features for smaller chip geometries such as yield optimisation and wireless/ RF design. The firm expects more users to move from L to XL with the growth of the 65nm chip industry.

The company expects Indian MNCs to adopt the platform. "Multinationals are increasingly driving their projects/ methodologies/tools/libraries from here. India is hence a very relevant market, said Mr Rahul Arya, Marketing Director, India and SAARC, Cadence Design Systems.

The Indian EDA market, as India Semiconductor Association reported recently, stands at $120 million.

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