The Hindu Business Line : Intel puts the squeeze on microchips

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Intel puts the squeeze on microchips

Unveils new architecture for nextgen 45-nm processor families

Anand Parthasarathy

This wide, this high! Intel Chief Executive, Mr Paul Otellini, seems to suggest the shape of technology to come, during media interaction at the chip leader’s annual developer forum in San Francisco on Tuesday. —

Anand Parthasarathy San Francisco, Sept. 19 The saga of the Incredible Shrinking Microchip continues apace: At its annual developer event that opened here on Tuesday, the world’s number one chip maker, Intel, previewed technology that will squeeze next year’s processors into even tighter configurations, to a new 45 nanometer fabrication standard, codenamed Penryn.

When coupled with a new micro-architecture — Nehalem — this will effectively put over 730 million transistors on every matchbox-sized slab of silicon, that will, for a start, fuel high performance computers and high-end servers in late 2008.

The company reiterated its commitment to churn out chips to a ‘tick-tock’ timetable that shrinks the fabrication tolerance every other year.

Retooling fabs

Fabs — jargon for silicon foundries — in Oregon and Arizona in the US were already retooled for starting full scale manufacture to the 45 nm standard, while new plants will come up next year in New Mexico (US) and Israel to add manufacturing capacity, announced the Chief Executive, Mr Paul Otellini, in his opening keynote.

As portable PCs like laptops and notebooks seemed poised to overtake global sales of desktop computers, he predicted: “The future of ultra mobility is a lot closer than we think.”

Over 120 trials in mobile WiMax technology were going on, worldwide, even now, Mr Otellini added.

The company also promised a new era of ‘green chips’: By end 2008, Intel’s semiconductor products would be both lead and halogen free.

32-nm tolerance chips

In a not-so-subtle hint that it was surging ahead of the competition, Intel also previewed the industry’s first-ever realisation of a silicon wafer — containing static random access memory chips — made to a 32-nanometer tolerance. Each chip held 1.9 billion transistors or gates. Chips to this tolerance were not expected till 2009.

A surprise presence at the conference was Intel co-founder and semiconductor visionary, Dr Gordon Moore, author of “Moore’s Law” that predicted the doubling of processor power every 18 to 24 months.

In a live interview by Dr Moira Gunn, host of the (US) National Pubic Radio show ‘Tech Nation’, Dr Moore said like any physical process, the processor roadmap suggested by his ‘law’ had to hit a final block – but he did not see this happening for 10-15 years.