Likely to be located in Pune at an estimated cost of Rs 400 cr

R. Ramachandran

Mean machine


To develop

home-grown high performance computing solutions

Uses a new

theory of interconnects based on the mathematical principles of `projective geometry'

System to outperform

fastest machines like Blue Gene of IBM

New Delhi, May 5

The Tata Group is likely to float a new company whose focus will be top-end supercomputers, according to reliable sources in the group.

The first initiative of this new venture, in which the Group Chairman, Mr Ratan Tata, is said to have taken personal interest, will be to build a machine based on a parallel supercomputing architecture that Prof Narendra Krishna Karmakar, the well-known Indian computer scientist, has claimed to have developed.

To an e-mail query on the venture, the Group's official spokesperson merely stated after persistent requests for a response:

"We are supporting a programme for developing home-grown High Performance Computing (HPC) solutions. We believe this would be an issue of national interest in the field of computer sciences. It is too premature to offer any details."

Back to high-end

Tata's foray into high-end computing systems is not new. The group had set up Tata Elxsi to manufacture mainframe computers, which, however, did not do too well in the market.

In recent years, the company has moved away from hardware and its focus has been in software services and providing system solutions.

The supercomputer project is estimated to cost Rs 400 crore and the group plans to invest about $140 million in the venture.

The proposal was apparently cleared after a technical and business evaluation by the Tata Strategic Management Group, the independent management consulting division of Tata Industries.

The new company may be located in Pune and, according to sources, will be headed by Prof Karmarkar and Dr Sunil Sherlekar of Tata Consultancy Services (TCS) in Bangalore. Prof Karmarkar and Dr Sherlekar were colleagues at IIT Bombay as students.

Prof Karmarkar resigned from the Tata Institute of Fundamental Research (TIFR), Mumbai, about a month ago as TIFR was unable to fund his mega project.

Prof Karmarkar was heading the Computational Mathematics Laboratory (CML) that the TIFR specially set up in Pune for his research work.

In a letter that Prof Karmarkar wrote to TIFR authorities on February 1, he claimed that even though TIFR did not support his project, he had completed the basic design of the supercomputing system with funding from Mr Tata and the Infosys Chairman, Mr N.R. Narayana Murthy.

Incidentally, Mr Tata is also the Chairman of the TIFR Council.

Prof Karmarkar had wanted the hardware costs (about Rs 400 crore) to be borne by TIFR immediately so that the new machine could compete in the forthcoming supercomputer benchmarking exercise of IEEE (Institute of Electrical and Electronic Engineers) and ACM (Association for Computing Machinery) in October.

"How could TIFR fund to this level over just one year when the total Plan Budget for the entire Plan period is only Rs 230 crore and that, too, when there is not even a detailed project proposal to evaluate its feasibility," pointed out the TIFR Dean.

Perhaps concerned about protecting his proprietary design ideas, which have been developed over the years, Prof Karmarkar has revealed little of the system details so far.

Limiting factor

A key limiting factor in achieving very high computational speeds in current HPC parallel architectures is the bottleneck caused by the numerous interconnects between the many parallel processors.

The new architecture, according to its inventor, Prof Karmarkar, uses a new theory of interconnects based on the mathematical principles of `projective geometry' to overcome the problem.

He has claimed that the machine built on this new architecture will outperform the fastest machines of today like the Blue Gene of IBM, which has a sustained computational speed of 280-300 teraflops (a trillion or 1012 floating point operations per second), and will aim to achieve a performance of petaflops (1015 flops).

Chip design

The design will make use of the off-the-shelf fast 64-bit processors (of Itanium 2 family) developed jointly by Hewlett-Packard and Intel.

Intel and HP, according to Prof Karmarkar, would also assist in system integration, if the HP-Intel processor is used.

The implementation of the interconnect architecture will, however, be done using a new high-speed switching chip made in Israel.

This chip has apparently been developed by an Indian computer scientist.

(This article was published in the Business Line print edition dated May 6, 2006)
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