Bangalore, Oct. 11
Electronic design automation software vendor Synopsys introduced MinChip - a tool that analyses physical design complexity and identifies the smallest routable size for semiconductor designs.
It is integrated into the physical design flow in Synopsys' JupiterXT floorplanning tool and IC Compiler place-and-route solution. MinChip automates the process of identifying the smallest routable area for a design. Optimal results are achieved in hours, saving weeks of manual effort while taking into account all potential area savings.
Following optimisation by IC Compiler, MinChip technology is applied to the design. In hours, it returns a result that represents the minimum area in which the design can be implemented and remain routable while retaining the characteristics of the original floorplan. The resulting design is then taken through the normal design closure process. In internal testing at Synopsys using customer taped out designs, average area reductions of nine per cent were observed, said the release issued by the company.