• Investment World
• eWorld
• Brand Line
• Mentor
• Life
• Canvas
• Praxis
• Urban Pulse
• Brand Quest
• The New Manager

Stocks

• Quotes
• SE Diary
• Scoreboard
• Open-End Mutual Fund

Shipping

• Ports
  
  

Archives

• Yesterday
• Datewise
• Resources

Group Sites

• The Hindu
• Business Line
• Sportstar
• Frontline
• The Hindu eBooks
• The Hindu Images

Our Bureau

Bangalore, March 22

Engineering software firm Synopsys Inc announced that its VCSÒ Verification Library, containing DesignWare verification intellectual property, is the first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual for SystemVerilog, published by Springer Science+Business Media. Verification engineers who use SystemVerilog for testbench development now have access to a proven portfolio of Synopsys verification intellectual property to decrease the cost of testbench development, speed the time to reach coverage goals, and reduce risk in order to meet project schedules, said the release.

More Stories on : New Products & Services | Software

Article E-Mail :: Comment :: Syndication :: Printer Friendly Page

Stories in this Section
RCoVL FCCB conversion at Rs 480.68 per share

Copyright © 2006, The Hindu Business Line. Republication or redissemination of the contents of this screen are expressly prohibited without the written consent of The Hindu Business Line